1. Field of the Invention
The present invention relates to a phase lock loop (PLL) circuit having a variable output frequency. More particularly, the present invention consists of an improved method for a fast and automatic setting of the output frequency of PLL synthesizers that overcomes the classical problems associated with prior implementations, concerning: linearity, locking range limitation, settling time, jitter, phase noise, and spectral purity deterioration.
2. Description of the Prior Art
A PLL synthesizer is a circuit used to generate a periodic signal with a precise frequency. This kind of circuit is widely used in many communication and measurement products. Its applications include advanced digital systems, such as microprocessors and micro-controllers. The PLL circuits should be designed with stringent constraints in terms of noise performance, settling time, power consumption, locking range, integration, cost, etc.
Typically PLLs include: a phase detector that compares the phase of the reference signal to the phase of an internal feedback signal; a charge pump and a low pass loop filter for setting an analogue voltage proportional to the detected phase difference; a voltage-controlled oscillator (VCO) that generates a periodic output signal with a frequency proportional to its input voltage; and a frequency divider that generates the feedback signal after dividing the frequency of the output signal by a predefined integer or fractional number (N).
Two seemingly contradictory requirements constitute the fundamental forces driving the design of VCOs. On one hand, a wide frequency tuning range and thus a high VCO gain are needed to compensate temperature and process variations and to cover the frequency band of the considered application. At the same time, the gain of the VCO should be as small as possible to meet phase noise and spectral purity specifications. In fact, the higher the gain of a VCO, the more its sensitivity to the noise in its control path increases. The VCO control path is in general affected by several noise sources that include: charge pump noise, filter noise and ripple due to mismatching between the charge pump up and down currents. The noise in the signal path generated by the active elements of the VCO is also dramatically amplified and converted to the phase noise if the VCO gain is high.
Some approaches for simultaneously reducing the VCO gain and enabling a wide frequency range were recently presented as for example in U.S. Pat. No. 5,942,949, U.S. Pat. No. 6,574,288 and U.S. Pub. No. 2003/0119467. All these solutions consist in breaking the wide range tuning curve into several narrower-range sections with some frequency overlap. A digital calibration of a switched-capacitor network is used to choose the appropriate narrow-range section before starting an analogue fine frequency tuning over this curve.
Additional blocks are needed to build a second loop, which achieves the digital self-calibration of the VCO. The second loop is generally constituted by a phase/frequency detector, a charge pump followed by a capacitor or a digital accumulator, and a state machine that applies a sequence of digital control input values to the VCO. The complexity of those extra blocks increases proportionally to the needed accuracy of the output frequency. Moreover, since the consecutive digital control words (e.g. 11110 and 00001) can use totally different units of the switched capacitor network, the accumulated capacitance errors due to process variation can reach very high values. Therefore, a very high frequency overlap is required to compensate these errors, leading to a higher gain of the VCO, a lower total tuning range, and a higher parasitic capacitance. This is why digital calibration can result in prolonged design cycles with a significant additional area and increased system costs.
This digital self-calibration is in general implemented with a simple algorithm such as sequential search as well as with more complex ones such as binary search. However, the time needed for those searching algorithms to achieve a fine resolution is often so high that only a coarse tuning or a self-calibration during the power up of the system is possible. Many side effects can affect the PLL output frequency during its on-mode such as temperature variation, power supply fluctuation, injection pulling etc. Therefore if the frequency varies significantly during the on-mode of the system, the PLL is not able to correct this variation within a reasonable time. Moreover, the PLL settling time is one of the most important criteria for many applications. It is even the most critical figure for systems dedicated to fast frequency-hopped spread-spectrum, Ultra-Wideband, data recovery or time-multiplexed transceivers. Therefore, already at the top-level system design it would be desirable to avoid the classical scheme, where a digital calibration for the first course tuning of the frequency is used, followed by a continuous tuning for the final fine adjustment of the frequency. This classical scheme constitutes the basis of the methods described in U.S. Pat. No. 6,574,288 and U.S. Pub. No. 2003/0119467. For the fine continuous tuning a reverse-biased diode, nMOS or pMOS varactor are typically used. However an integrated circuit is disclosed in U.S. Pat. No. 6,574,288 and U.S. Pub. No. 2003/0119467 enabling to avoid the use of these traditional varactors during the fine-tuning stage. In this circuit, capacitors with fixed values are used in an implementation where each capacitor is linked to a variable impedance device. The variable impedance devices are transistors having their gate controlled by a plurality of analogue signals. The equivalent capacitance of the circuit is indirectly varied by varying the impedance of the variable impedance devices. To avoid the abrupt nonlinear variation of the impedances an offset voltage is introduced between the control analogue signals. However, if a fast and fine resolution self-calibration technique is available, it enables operation very close to the desired frequency. In this way the use of the noisy and cumbersome variable impedance devices, capacitors and their control circuitry can be avoided, and only a small varactor (pn junction, nMOS or pMOS) is sufficient to achieve the final fine-tuning. Moreover, the gain of the VCO is at its minimum during the operation of the system and the noise performance is significantly improved.